Conventionally, a PLL circuit comprises a voltage controlled oscillator, a phase error detector for detecting a phase error between an output of the voltage controlled oscillator and an external reference signal, and a loop filter inserted between an error signal output of the phase error detector and a control voltage input of the voltage controlled oscillator. A frequency divider may be provided between the output of the oscillator and an input of the phase error detector.
As shown in FIG. 1, a loop filter in a conventional PLL comprises a charge pump CP which is directly controlled by an error signal from a phase error detector PED and an RC series combination which is connected between a fixed supply terminal on the one hand and a connecting node between the current output of the charge pump CP and the control input of the voltage controlled oscillator VCO, on the other hand. The phase error detector PED has a first input receiving a reference frequency signal ƒin and a second input receiving the output of a frequency divider DIV, the input of which is connected to the output of the voltage controlled oscillator VCO. The output of voltage controlled oscillator VCO is the desired output signal of frequency ƒout. The control voltage VVCO of the oscillator VCO in such a circuit is given by
                                          V            VCO                    =                                                    1                C                            ⁢              It                        +            RI                          ,                            (        1        )            wherein C is the capacity and R is the resistance of the RC series combination, I is the current from the charge pump CP and t is the time.
Usually, for low bandwidth PLLs, if the capacitor C is formed on chip, it often covers more than 70% of the whole PLL circuit area. It would therefore be desirable to be able to reduce the capacitor area and, thus, the chip size. However, there is a problem in that the damping and bandwidth of the PLL circuit depend on the size of the capacitor C. Damping is given by
                              s          =                                    1              2                        ⁢                                                                                IK                    VCO                                    ⁢                                      R                    2                                    ⁢                  C                                N                                                    ,                            (        2        )            wherein KVCO is the gain of the voltage-controlled oscillator, and N is the dividing ratio of frequency divider DIV.
Bandwidth is given by
                              ω          n                =                                                            IK                VCO                            NC                                .                                    (        3        )            
It is readily apparent that if the capacitor is to be reduced without reducing damping and bandwidth, it is necessary to increase the resistance R. An increased resistor value has several disadvantages. Matching becomes difficult, and the effect of thermal noise also increases.
So-called self-biased PLL circuits have a loop filter, which comprises two identical charge pumps in parallel. Instead of an RC series combination, there is a capacitor connected to the current output of one of the charge pumps and a resistor connected to the current output of the other. For a given damping and bandwidth, the values of capacitor and resistor are the same as for a conventional loop filter having a single charge pump.